Showing posts with label OSN3500. Show all posts
Showing posts with label OSN3500. Show all posts

Thursday, May 27, 2021

Why EGS4 prevents LACP protocol packets from being transparently transmitted?

 Problem Description

The link aggregation function is activated between two switches in a certain office. One port uses the dedicated line service configured by EGS4 and EGS2 of OSN3500, and the other port uses optical fiber to connect directly. When the switch starts manual aggregation (without LACP protocol), the service is normal. But when it is configured as static aggregation (LACP protocol is started), the service fails. The attributes of the external ports of the EGS4 and EGS2 boards are Hybrid. The switch on the EGS4 side can receive LACP packets, but the EGS2 switch cannot receive LACP packets.




Warning message


No abnormal transmission alarm


Process


1. Since the business is normal when using manual aggregation, it is certain that there is no problem with the transmission channel.

2. The difference between static aggregation and manual aggregation is that it uses the LACP protocol. Therefore, when static aggregation is suspected, the cause of service failure is that LACP protocol packets are not transparently transmitted to the peer device.

3. The LACP protocol does not have a VLAN tag. It should be no problem if the port attribute is set to Hybrid. It is suspected that the ingress port of the egs4 board does not transparently transmit LACP packets.

4. After confirming that the egs4 board supports the LACP protocol, when the external port receives the LACP message, it will be sent to the CPU for processing instead of transparently transmitting the LACP message. In this case, you need to set the port's "ingress detection" function as "Prohibited"

5. The static link aggregation service of the switch is normally opened after setting the "ingress detection" of the port


Root cause


1. The EGS4 board supports the LACP protocol. When the external port receives the LACP message, it will be sent to the CPU for processing and will not transparently transmit the LACP message. If the LACP message needs to be transparently transmitted, it is necessary to set the port's "ingress detection" "The function is "Prohibited".

2. The EGS2 board port does not support the LACP protocol, and treats LACP packets as ordinary Ethernet packets, so LACP packets can be detected in one direction.


Conclusions


At the same time, I learned that SSN5EFS0 also has this problem. When you need to transparently transmit LACP packets, you need to pay attention to the "ingress detection" attribute configuration.

Tuesday, November 13, 2018

What is the Working Principle and Signal Flow of Huawei STM-4 service board SLD4A?

SLD4A consists of the O/E converting module, CDR module, SDH overhead processing module, logic and control module, and power module. 
SLD4A can apply to Huawei MSTP equipment OSN1500B, OSN2500, OSN3500 and OSN7500.

Figure 1 shows the functional block diagram of the SLD4A.
Figure 1 Functional block diagram of the SLD4A
The functional modules of the STM-4 units are described as follows:

O/E Converting Module

  • Converts the received optical signals into electrical signals, in the receive direction.
  • Converts the electrical signals into SDH optical signals, and then sends the SDH optical signals to fibers for transmission, in the transmit direction.
  • The SPI detects the R_LOS alarm and provides the laser shut down function.

CDR Module

This module restores the clock signal.

SDH Overhead Processing Module

this module includes the RST, MST, MSA, and HPT sub-modules. This module provides the inloop and outloop functions.
  • RST sub-module
    • In the receive direction, the RST sub-module terminates the regenerator section overhead (RSOH). That is, the RST sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes except the first line of the RSOH, restores and checks the regenerator section trace byte (J0), and checks the B1 byte.
    • In the transmit direction, the RST sub-module generates the RSOH. That is, the RST sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and scrambles all the bytes except the first line of the RSOH.
  • MST sub-module
    • In the receive direction, the MST sub-module terminates the multiplex section overhead (MSOH). That is, the MST sub-module generates the multiplex section-alarm indication signal (MS_AIS) alarm and detects the multiplex section-remote defect indication (MS_RDI) alarm after detecting the K2 byte, and detects the multiplex section-remote error indication (MS_REI) alarm and generates the B2-excessive errors (B2_EXC) alarm after checking the B2 byte.
    • In the transmit direction, the MST sub-module generates the MSOH. That is, the MST sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and writes the B2 byte.
  • MSA sub-module
    • In the receive direction, the MSA sub-module de-interleaves the administration unit group (AUG), divides an AUG into N AU-4s, detects the administration unit-loss of pointer (AU_LOP) alarm and the administration unit-alarm indication signal (AU_AIS) alarm, and performs pointer justifications.
    • In the transmit direction, the MSA sub-module assembles the AUG and generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
  • HPT sub-module
    • In the receive direction, the HPT sub-module terminates the path overhead (POH). That is, the HPT sub-module detects the higher order path-remote error indication (HP_REI) alarm after checking the B3 byte, generates the higher order path-trace identifier mismatch (HP_TIM) alarm and the higher order path-signal label mismatch (HP_SLM) alarm and detects the higher order path-remote defect indication (HP_RDI) alarm after detecting the J1 and C2 bytes, and generates the higher order path-unequipped (HP_UNEQ) alarm after detecting the C2 byte.
    • In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-module writes bytes such as J1 and C2, and calculates and writes the B3 byte.

Logic and Control Module

  • Manages and configures the other modules of the board.
  • Performs inter-board communication through the internal Ethernet interface.
  • Traces the clock signal from the active and standby cross-connect units.
  • Controls the laser.
  • Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when the GSCC is not in position.
  • Selects the clock signal and frame header signal from the active and standby cross-connect units.
  • Controls the indicators on the board.

Power Module

It converts the –48 V/–60 V power supply into the DC voltages that the modules of the board require.